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Unsigned rounding shift right by immediate.

Shift right by immediate each active unsigned element of the source vector, and destructively place the rounded results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.



URSHR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>

if !HaveSVE2() then UNDEFINED;
bits(4) tsize = tszh:tszl;
case tsize of
    when '0000' UNDEFINED;
    when '0001' esize = 8;
    when '001x' esize = 16;
    when '01xx' esize = 32;
    when '1xxx' esize = 64;
integer g = UInt(Pg);
integer dn = UInt(Zdn);
integer shift = (2 * esize) - UInt(tsize:imm3);

Assembler Symbols


Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T> Is the size specifier, encoded in tszh:tszl:
tszh tszl <T>
00 01 B
00 1x H
01 xx S
1x xx D

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.


Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3".


integer elements = VL DIV esize;
bits(VL) operand1 = Z[dn];
bits(PL) mask = P[g];
bits(VL) result;
integer round_const = 1 << (shift-1);

for e = 0 to elements-1
    integer element1 = UInt(Elem[operand1, e, esize]);
    if ElemP[mask, e, esize] == '1' then
        integer res = (element1 + round_const) >> shift;
        Elem[result, e, esize] = res<esize-1:0>;
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn] = result;