LDRH (register)
Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | Rm | option | S | 1 | 0 | Rn | Rt | ||||||||||||||
size | opc |
if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer shift = if S == '1' then 1 else 0;
For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<Wt> |
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Wm> |
When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field. |
<Xm> |
When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field. |
<amount> |
Is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S:
|
Operation
bits(64) offset = ExtendReg(m, extend_type, shift); if HaveMTEExt() then SetNotTagCheckedInstruction(FALSE); bits(64) address; bits(16) data; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; address = address + offset; data = Mem[address, 2, AccType_NORMAL]; X[t] = ZeroExtend(data, 32);
Operational information
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.