CLASTA (SIMD&FP scalar)
Conditionally extract element after last to SIMD&FP scalar register.
From the source vector register extract the element after the last active element, or if the last active element is the final element extract element zero, and then zero-extend that element to destructively place in the destination and first source SIMD & floating-point scalar register. If there are no active elements then destructively zero-extend the least significant element-size bits of the destination and first source SIMD & floating-point scalar register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | Pg | Zm | Vdn |
if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Vdn); integer m = UInt(Zm); boolean isBefore = FALSE;
Assembler Symbols
<V> |
Is a width specifier,
encoded in
size:
|
<dn> |
Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field. |
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zm> |
Is the name of the source scalable vector register, encoded in the "Zm" field. |
<T> |
Is the size specifier,
encoded in
size:
|
Operation
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(esize) operand1 = V[dn]; bits(VL) operand2 = Z[m]; bits(esize) result; integer last = LastActiveElement(mask, esize); if last < 0 then result = ZeroExtend(operand1); else if !isBefore then last = last + 1; if last >= elements then last = 0; result = Elem[operand2, last, esize]; V[dn] = result;
Operational information
If PSTATE.DIT is 1:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
- The values of the NZCV flags.