SUBHN, SUBHN2
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
The results are truncated. For rounded results, see RSUBHN.
The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | Rm | 0 | 1 | 1 | 0 | 0 | 0 | Rn | Rd | |||||||||||||
U | o1 |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '11' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; boolean sub_op = (o1 == '1'); boolean round = (U == '1');
Assembler Symbols
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Tb> |
Is an arrangement specifier,
encoded in
size:Q:
|
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Ta> |
Is an arrangement specifier,
encoded in
size:
|
<Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
Operation
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
Operational information
If PSTATE.DIT is 1:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.