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## SBCLB

Subtract with carry long (bottom).

Subtract the even-numbered elements of the first source vector and the inverted 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector from the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 1 1 sz 0 Zm 1 1 0 1 0 0 Zn Zda

#### SVE2

SBCLB <Zda>.<T>, <Zn>.<T>, <Zm>.<T>

```if !HaveSVE2() then UNDEFINED;
integer esize = 32 << UInt(sz);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer da = UInt(Zda);```

### Assembler Symbols

 Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
<T> Is the size specifier, encoded in sz:
sz <T>
0 S
1 D
 Is the name of the first source scalable vector register, encoded in the "Zn" field.
 Is the name of the second source scalable vector register, encoded in the "Zm" field.

### Operation

```CheckSVEEnabled();
integer pairs = VL DIV (esize * 2);
bits(VL) operand = Z[n];
bits(VL) carries = Z[m];
bits(VL) result = Z[da];

for p = 0 to pairs-1
bits(esize) element1 = Elem[result, 2*p + 0, esize];
bits(esize) element2 = Elem[operand, 2*p + 0, esize];
bit carry_in = Elem[carries, 2*p + 1, esize]<0>;

(res, nzcv) = AddWithCarry(element1, NOT(element2), carry_in);
carry_out = nzcv<1>;

Elem[result, 2*p + 0, esize] = res;
Elem[result, 2*p + 1, esize] = ZeroExtend(carry_out);

Z[da] = result;```

### Operational information

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
• The values of the data supplied in any of its registers.
• The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
• The values of the data supplied in any of its registers.
• The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:

• The MOVPRFX instruction must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.
The MOVPRFX instructions that can be used with this instruction are as follows:
• An unpredicated MOVPRFX instruction.