You copied the Doc URL to your clipboard.

SPLICE

Splice two vectors under predicate control.

Copy the first active to last active elements (inclusive) from the first source vector to the lowest-numbered elements of the result. Then set any remaining elements of the result to a copy of the lowest-numbered elements from the second source vector. The result is placed destructively in the destination and first source vector, or constructively in the destination vector.

It has encodings from 2 classes: Constructive and Destructive

Constructive

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 size 1 0 1 1 0 1 1 0 0 Pg Zn Zd

Constructive

SPLICE <Zd>.<T>, <Pg>, { <Zn1>.<T>, <Zn2>.<T> }

```if !HaveSVE2() then UNDEFINED;
integer esize = 8 << UInt(size);
integer g = UInt(Pg);
integer dst = UInt(Zd);
integer s1 = UInt(Zn);
integer s2 = (s1 + 1) MOD 32;```

Destructive

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 size 1 0 1 1 0 0 1 0 0 Pg Zm Zdn

Destructive

SPLICE <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>

```if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer g = UInt(Pg);
integer dst = UInt(Zdn);
integer s1 = dst;
integer s2 = UInt(Zm);```

Assembler Symbols

 Is the name of the destination scalable vector register, encoded in the "Zd" field.
 Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D
 Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 Is the name of the first scalable vector register of a multi-vector sequence, encoded in the "Zn" field.
 Is the name of the second scalable vector register of a multi-vector sequence, encoded in the "Zn" field.
 Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

```CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand1 = Z[s1];
bits(VL) operand2 = Z[s2];
bits(VL) result;
integer x = 0;
boolean active = FALSE;

if lastnum >= 0 then
for e = 0 to lastnum
active = active || ElemP[mask, e, esize] == '1';
if active then
Elem[result, x, esize] = Elem[operand1, e, esize];
x = x + 1;

elements = elements - x - 1;
for e = 0 to elements
Elem[result, x, esize] = Elem[operand2, e, esize];
x = x + 1;

Z[dst] = result;```

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

• The MOVPRFX instruction must be unpredicated.
• The MOVPRFX instruction must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.