Arm® A64 Instruction Set Architecture: Future Architecture Technologies in the A architecture profile

AESIMC

AES inverse mix columns.

The AESIMC instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the InvMixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.

ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.

if !HaveSVE2AES() then UNDEFINED;
integer dn = UInt(Zdn);

Assembler Symbols

CheckSVEEnabled();
integer segments = VL DIV 128;
bits(VL) operand = Z[dn];
bits(VL) result;

for s = 0 to segments-1
    Elem[result, s, 128] = AESInvMixColumns(Elem[operand, s, 128]);

Z[dn] = result;

Operational information

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.