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## FCVTX

Floating-point down convert, rounding to odd (predicated).

Convert active double-precision floating-point elements from the source vector to single-precision, rounding to Odd, and place the results in the even-numbered 32-bit elements of the destination vector, while setting the odd-numbered elements to zero. Inactive elements in the destination vector register remain unmodified.

Rounding to Odd (aka Von Neumann rounding) permits a two-step conversion from double-precision to half-precision without incurring intermediate rounding errors.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 Pg Zn Zd

#### Double-precision to single-precision

FCVTX <Zd>.S, <Pg>/M, <Zn>.D

```if !HaveSVE2() then UNDEFINED;
integer esize = 64;
integer g = UInt(Pg);
integer n = UInt(Zn);
integer d = UInt(Zd);
integer s_esize = 64;
integer d_esize = 32;```

### Assembler Symbols

 Is the name of the destination scalable vector register, encoded in the "Zd" field.
 Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 Is the name of the source scalable vector register, encoded in the "Zn" field.

### Operation

```CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand  = Z[n];
bits(VL) result = Z[d];

for e = 0 to elements-1
bits(esize) element = Elem[operand, e, esize];
if ElemP[mask, e, esize] == '1' then
bits(d_esize) res = FPConvertSVE(element<s_esize-1:0>, FPCR<31:0>, FPRounding_ODD);
Elem[result, e, esize] = ZeroExtend(res);

Z[d] = result;```

### Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

• The MOVPRFX instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.
• The MOVPRFX instruction must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.