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FCVTLT

Floating-point up convert long (top, predicated).

Convert odd-numbered floating-point elements from the source vector to the next higher precision, and place the results in the active overlapping double-width elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

It has encodings from 2 classes: Half-precision to single-precision and Single-precision to double-precision

Half-precision to single-precision

313029282726252423222120191817161514131211109876543210
0110010010001001101PgZnZd

FCVTLT <Zd>.S, <Pg>/M, <Zn>.H

if !HaveSVE2() then UNDEFINED;
integer esize = 32;
integer g = UInt(Pg);
integer n = UInt(Zn);
integer d = UInt(Zd);

Single-precision to double-precision

313029282726252423222120191817161514131211109876543210
0110010011001011101PgZnZd

FCVTLT <Zd>.D, <Pg>/M, <Zn>.S

if !HaveSVE2() then UNDEFINED;
integer esize = 64;
integer g = UInt(Pg);
integer n = UInt(Zn);
integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

CheckSVEEnabled();
integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand  = Z[n];
bits(VL) result = Z[d];

for e = 0 to elements-1
    if ElemP[mask, e, esize] == '1' then
        bits(esize DIV 2) element = Elem[operand, 2*e + 1, esize DIV 2];
        Elem[result, e, esize] = FPConvertSVE(element, FPCR);

Z[d] = result;