LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH
Atomic bit clear on halfword in memory atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.
- If the destination register is not WZR, LDCLRAH and LDCLRALH load from memory with acquire semantics.
- LDCLRLH and LDCLRALH store to memory with release semantics.
- LDCLRH has neither acquire nor release semantics.
For more information about memory ordering semantics see Load-Acquire, Store-Release.
For information about memory accesses see Load/Store addressing modes.
This instruction is used by the alias STCLRH, STCLRLH.
if !HaveAtomicExt() then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; boolean tag_checked = n != 31;
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
|Alias||Is preferred when|
|STCLRH, STCLRLH||A == '0' && Rt == '11111'|
bits(64) address; bits(16) value; bits(16) data; if HaveMTEExt() then SetTagCheckedInstruction(tag_checked); value = X[s]; if n == 31 then CheckSPAlignment(); address = SP; else address = X[n]; data = MemAtomic(address, MemAtomicOp_BIC, value, ldacctype, stacctype); if t != 31 then X[t] = ZeroExtend(data, 32);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.