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AArch64 Functions.Tme Pseudocode
Library pseudocode for aarch64/functions/tme/CheckTMEEnabled
// CheckTMEEnabled() // ================= // Returns TRUE if access to TME instruction is enabled, FALSE otherwise. CheckTMEEnabled() if PSTATE.EL IN {EL0, EL1, EL2} && HaveEL(EL3) then if SCR_EL3.TME == '0' then UNDEFINED; if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then if HCR_EL2.TME == '0' then UNDEFINED; return;
Library pseudocode for aarch64/functions/tme/CheckTransactionalSystemAccess
// CheckTransactionalSystemAccess() // ================================ // Returns TRUE if an AArch64 MSR, MRS, or SYS instruction is permitted in // Transactional state, based on the opcode's encoding, and FALSE otherwise. boolean CheckTransactionalSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bit read) case read:op0:op1:crn:crm:op2 of when '0 00 011 0100 xxxx 11x' return TRUE; // MSR (imm): DAIFSet, DAIFClr when '0 01 011 0111 0100 001' return TRUE; // DC ZVA when '0 11 011 0100 0010 00x' return TRUE; // MSR: NZCV, DAIF when '0 11 011 0100 0100 00x' return TRUE; // MSR: FPCR, FPSR when '0 11 000 0100 0110 000' return TRUE; // MSR: ICC_PMR_EL1 when '0 11 011 1001 1100 100' return TRUE; // MRS: PMSWINC_EL0 when '1 11 xxx 0xxx xxxx xxx' return TRUE; // MRS: op1=3, CRn=0..7 when '1 11 xxx 100x xxxx xxx' return TRUE; // MRS: op1=3, CRn=8..9 when '1 11 xxx 1010 xxxx xxx' return TRUE; // MRS: op1=3, CRn=10 when '1 11 000 1100 1x00 010' return TRUE; // MRS: op1=3, CRn=12 - ICC_HPPIRx_EL1 when '1 11 000 1100 1011 011' return TRUE; // MRS: op1=3, CRn=12 - ICC_RPR_EL1 when '1 11 xxx 1101 xxxx xxx' return TRUE; // MRS: op1=3, CRn=13 when '1 11 xxx 1110 xxxx xxx' return TRUE; // MRS: op1=3, CRn=14 when 'x 11 xxx 1x11 xxxx xxx' return boolean IMPLEMENTATION_DEFINED; // MRS: op1=3, CRn=11,15 otherwise return FALSE; // all other SYS, SYSL, MRS, MSR
Library pseudocode for aarch64/functions/tme/CommitTransactionalWrites
// Makes all transactional writes to memory observable by other PEs and reset // the transactional read and write sets. CommitTransactionalWrites();
Library pseudocode for aarch64/functions/tme/DiscardTransactionalWrites
// Discards all transactional writes to memory and reset the transactional // read and write sets. DiscardTransactionalWrites();
Library pseudocode for aarch64/functions/tme/FailTransaction
// FailTransaction() // ================= FailTransaction(TMFailure cause, boolean retry) FailTransaction(cause, retry, FALSE, Zeros(15)); return; // FailTransaction() // ================= // Exits Transactional state and discards transactional updates to registers // and memory. FailTransaction(TMFailure cause, boolean retry, boolean interrupt, bits(15) reason) assert !retry || !interrupt; DiscardTransactionalWrites(); RestoreTransactionCheckpoint(); ClearExclusiveLocal(ProcessorID()); bits(64) result = Zeros(); result<23> = if interrupt then '1' else '0'; result<15> = if retry && !interrupt then '1' else '0'; case cause of when TMFailure_DBG result<22> = '1'; when TMFailure_NEST result<21> = '1'; when TMFailure_SIZE result<20> = '1'; when TMFailure_ERR result<19> = '1'; when TMFailure_IMP result<18> = '1'; when TMFailure_MEM result<17> = '1'; when TMFailure_CNCL result<16> = '1'; result<14:0> = reason; TSTATE.depth = 0; X[TSTATE.Rt] = result; BranchTo(TSTATE.nPC, BranchType_TMFAIL); EndOfInstruction(); return;
Library pseudocode for aarch64/functions/tme/RestoreTransactionCheckpoint
// RestoreTransactionCheckpoint() // ============================== // Restores part of the PE registers from the transaction checkpoint. RestoreTransactionCheckpoint() SP[] = TSTATE.SP; ICC_PMR_EL1 = TSTATE.ICC_PMR_EL1; PSTATE.<N,Z,C,V> = TSTATE.nzcv; PSTATE.<D,A,I,F> = TSTATE.<D,A,I,F>; for n = 0 to 30 X[n] = TSTATE.X[n]; if IsFPEnabled(PSTATE.EL) then if IsSVEEnabled(PSTATE.EL) then for n = 0 to 31 Z[n] = TSTATE.Z[n]<VL-1:0>; for n = 0 to 15 P[n] = TSTATE.P[n]<PL-1:0>; FFR[] = TSTATE.FFR<PL-1:0>; else for n = 0 to 31 V[n] = TSTATE.Z[n]<127:0>; FPCR = TSTATE.FPCR; FPSR = TSTATE.FPSR; return;
Library pseudocode for aarch64/functions/tme/StartTrackingTransactionalReadsWrites
// Starts tracking transactional reads and writes to memory. StartTrackingTransactionalReadsWrites();
Library pseudocode for aarch64/functions/tme/TMFailure
enumeration TMFailure { TMFailure_CNCL, // Executed a TCANCEL instruction TMFailure_DBG, // A debug event was generated TMFailure_ERR, // A non-permissible operation was attempted TMFailure_NEST, // The maximum transactional nesting level was exceeded TMFailure_SIZE, // The transactional read or write set limit was exceeded TMFailure_MEM, // A transactional conflict occurred TMFailure_TRIVIAL, // Only a TRIVIAL version of TM is available TMFailure_IMP // Any other failure cause };
Library pseudocode for aarch64/functions/tme/TMState
type TMState is (
integer depth, // Transaction nesting depth
integer Rt, // TSTART destination register
bits(64) nPC, // Fallback instruction address
array[0..30] of bits(64) X, // General purpose registers
array[0..31] of bits(MAX_VL) Z, // Vector registers
array[0..15] of bits(MAX_PL) P, // Predicate registers
bits(MAX_PL) FFR, // First Fault Register
bits(64) SP, // Stack Pointer at current EL
bits(32) FPCR, // Floating-point Control Register
bits(32) FPSR, // Floating-point Status Register
bits(32) ICC_PMR_EL1, // Interrupt Controller Interrupt Priority Mask Register
bits(4) nzcv, // Condition flags
bits(1) D, // Debug mask bit
bits(1) A, // SError interrupt mask bit
bits(1) I, // IRQ mask bit
bits(1) F // FIQ mask bit
)
Library pseudocode for aarch64/functions/tme/TakeTransactionCheckpoint
// TakeTransactionCheckpoint() // =========================== // Captures part of the PE registers into the transaction checkpoint. TakeTransactionCheckpoint() TSTATE.SP = SP[]; TSTATE.ICC_PMR_EL1 = ICC_PMR_EL1; TSTATE.nzcv = PSTATE.<N,Z,C,V>; TSTATE.<D,A,I,F> = PSTATE.<D,A,I,F>; for n = 0 to 30 TSTATE.X[n] = X[n]; if IsFPEnabled(PSTATE.EL) then if IsSVEEnabled(PSTATE.EL) then for n = 0 to 31 TSTATE.Z[n]<VL-1:0> = Z[n]; for n = 0 to 15 TSTATE.P[n]<PL-1:0> = P[n]; TSTATE.FFR<PL-1:0> = FFR[]; else for n = 0 to 31 TSTATE.Z[n]<127:0> = V[n]; TSTATE.FPCR = FPCR; TSTATE.FPSR = FPSR; return;
Library pseudocode for aarch64/functions/tme/TransactionStartTrap
// TransactionStartTrap() // ====================== // Traps the execution of TSTART instruction. TransactionStartTrap(integer dreg) bits(64) preferred_exception_return = ThisInstrAddr(); vect_offset = 0x0; exception = ExceptionSyndrome(Exception_TSTARTAccessTrap); exception.syndrome<9:5> = dreg<4:0>; if UInt(PSTATE.EL) > UInt(EL1) then targetEL = PSTATE.EL; elsif EL2Enabled() && HCR_EL2.TGE == '1' then targetEL = EL2; else targetEL = EL1; AArch64.TakeException(targetEL, exception, preferred_exception_return, vect_offset);