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Shuffle active elements of vector to the right and fill with zero.

Read the active elements from the source vector and pack them into the lowest-numbered elements of the destination vector. Then set any remaining elements of the destination vector to zero.


COMPACT <Zd>.<T>, <Pg>, <Zn>.<T>

if !HaveSVE() then UNDEFINED;
if size == '0x' then UNDEFINED;
integer esize = 8 << UInt(size);
integer g = UInt(Pg);
integer n = UInt(Zn);
integer d = UInt(Zd);

Assembler Symbols


Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.


Is the name of the source scalable vector register, encoded in the "Zn" field.


integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand1 = Z[n];
bits(VL) result;
integer x = 0;

for e = 0 to elements-1
    Elem[result, e, esize] = Zeros();
    if ElemP[mask, e, esize] == '1' then
        bits(esize) element = Elem[operand1, e, esize];
        Elem[result, x, esize] = element;
        x = x + 1;

Z[d] = result;