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LDNT1D (vector plus scalar)

Gather load non-temporal unsigned doublewords.

Gather load non-temporal of doublewords to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.

A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.


LDNT1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]

if !HaveSVE2() then UNDEFINED;
integer t = UInt(Zt);
integer n = UInt(Zn);
integer m = UInt(Rm);
integer g = UInt(Pg);
integer esize = 64;
integer msize = 64;
boolean unsigned = TRUE;

Assembler Symbols


Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.


Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.


Is the name of the base scalable vector register, encoded in the "Zn" field.


Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.


integer elements = VL DIV esize;
bits(VL) base = Z[n];
bits(64) offset = X[m];
bits(64) addr;
bits(PL) mask = P[g];
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;

if HaveMTEExt() then SetTagCheckedInstruction(TRUE);

for e = 0 to elements-1
    if ElemP[mask, e, esize] == '1' then
        addr = ZeroExtend(Elem[base, e, esize], 64) + offset;
        data = Mem[addr, mbytes, AccType_STREAM];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
        Elem[result, e, esize] = Zeros();

Z[t] = result;