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MSR (immediate)
Move immediate value to Special Register moves an immediate value to selected bits of the PSTATE. For more information, see Process state, PSTATE.
The bits that can be written by this instruction are:
- PSTATE.D, PSTATE.A, PSTATE.I, PSTATE.F, and PSTATE.SP.
- If ARMv8.0-SSBS is implemented, PSTATE.SSBS.
- If ARMv8.1-PAN is implemented, PSTATE.PAN.
- If ARMv8.2-UAO is implemented, PSTATE.UAO.
- If ARMv8.4-DIT is implemented, PSTATE.DIT.
- If ARMv8.5-MemTag is implemented, PSTATE.TCO.
- If FEAT_CSRE is implemented, PSTATE.CSR.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | op1 | 0 | 1 | 0 | 0 | CRm | op2 | 1 | 1 | 1 | 1 | 1 |
MSR <pstatefield>, #<imm>
if op1 == '000' && op2 == '000' then SEE "CFINV"; if op1 == '000' && op2 == '001' then SEE "XAFLAG"; if op1 == '000' && op2 == '010' then SEE "AXFLAG"; AArch64.CheckSystemAccess('00', op1, '0100', CRm, op2, '11111', '0'); bits(2) min_EL; boolean need_secure = FALSE; case op1 of when '00x' min_EL = EL1; when '010' min_EL = EL1; when '011' min_EL = EL0; when '100' min_EL = EL2; when '101' UNDEFINED; when '110' min_EL = EL3; when '111' min_EL = EL1; need_secure = TRUE; if UInt(PSTATE.EL) < UInt(min_EL) || (need_secure && !IsSecure()) then UNDEFINED; PSTATEField field; case op1:op2 of when '000 011' if !HaveUAOExt() then UNDEFINED; field = PSTATEField_UAO; when '000 100' if !HavePANExt() then UNDEFINED; field = PSTATEField_PAN; when '000 101' field = PSTATEField_SP; when '011 010' if !HaveDITExt() then UNDEFINED; field = PSTATEField_DIT; when '011 011' if CRm == '000x' then if !HaveCSRExt() then UNDEFINED; field = PSTATEField_CSR; else UNDEFINED; when '011 100' if !HaveMTEExt() then UNDEFINED; field = PSTATEField_TCO; when '011 110' field = PSTATEField_DAIFSet; when '011 111' field = PSTATEField_DAIFClr; when '011 001' if !HaveSSBSExt() then UNDEFINED; field = PSTATEField_SSBS; otherwise UNDEFINED; // Check that an AArch64 MSR/MRS access to the DAIF flags is permitted if PSTATE.EL == EL0 && field IN {PSTATEField_DAIFSet, PSTATEField_DAIFClr} then if !ELUsingAArch32(EL1) && ((EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') || SCTLR_EL1.UMA == '0') then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18);
Assembler Symbols
<pstatefield> |
Is a PSTATE field name,
encoded in
op1:op2:
|
<imm> |
Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field. |
Operation
case field of when PSTATEField_SSBS PSTATE.SSBS = CRm<0>; when PSTATEField_SP PSTATE.SP = CRm<0>; when PSTATEField_DAIFSet PSTATE.D = PSTATE.D OR CRm<3>; PSTATE.A = PSTATE.A OR CRm<2>; PSTATE.I = PSTATE.I OR CRm<1>; PSTATE.F = PSTATE.F OR CRm<0>; when PSTATEField_DAIFClr PSTATE.D = PSTATE.D AND NOT(CRm<3>); PSTATE.A = PSTATE.A AND NOT(CRm<2>); PSTATE.I = PSTATE.I AND NOT(CRm<1>); PSTATE.F = PSTATE.F AND NOT(CRm<0>); when PSTATEField_PAN PSTATE.PAN = CRm<0>; when PSTATEField_UAO PSTATE.UAO = CRm<0>; when PSTATEField_DIT PSTATE.DIT = CRm<0>; when PSTATEField_TCO PSTATE.TCO = CRm<0>; when PSTATEField_CSR PSTATE.CSR = CRm<0>;