Load-Acquire RCpc Register Signed Byte (unscaled) calculates an address from a base register and an immediate offset, loads a signed byte from memory, sign-extends it, and writes it to a register.
The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:
- There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction.
- The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed.
This difference in memory ordering is not described in the pseudocode.
For information about memory accesses, see Load/Store addressing modes.
bits(64) offset = SignExtend(imm9, 64);
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
integer n = UInt(Rn); integer t = UInt(Rt); MemOp memop; boolean signed; integer regsize; if opc<1> == '0' then // store or zero-extending load memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; regsize = 32; signed = FALSE; else // sign-extending load memop = MemOp_LOAD; regsize = if opc<0> == '1' then 32 else 64; signed = TRUE; boolean tag_checked = memop != MemOp_PREFETCH && (n != 31);
if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); bits(64) address; bits(8) data; if n == 31 then if memop != MemOp_PREFETCH then CheckSPAlignment(); address = SP; else address = X[n]; address = address + offset; case memop of when MemOp_STORE data = X[t]; Mem[address, 1, AccType_ORDERED] = data; when MemOp_LOAD data = Mem[address, 1, AccType_ORDERED]; if signed then X[t] = SignExtend(data, regsize); else X[t] = ZeroExtend(data, regsize); when MemOp_PREFETCH Prefetch(address, t<4:0>);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.