You copied the Doc URL to your clipboard.

ROR (immediate)

Rotate right (immediate) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.

This is an alias of EXTR. This means:

  • The encodings in this description are named to match the encodings of EXTR.
  • The description of EXTR gives the operational pseudocode for this instruction.

313029282726252423222120191817161514131211109876543210
sf00100111N0RmimmsRnRd

32-bit (sf == 0 && N == 0 && imms == 0xxxxx)

ROR <Wd>, <Ws>, #<shift>

is equivalent to

EXTR <Wd>, <Ws>, <Ws>, #<shift>

and is the preferred disassembly when Rn == Rm.

64-bit (sf == 1 && N == 1)

ROR <Xd>, <Xs>, #<shift>

is equivalent to

EXTR <Xd>, <Xs>, <Xs>, #<shift>

and is the preferred disassembly when Rn == Rm.

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Ws>

Is the 32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xs>

Is the 64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.

<shift>

For the 32-bit variant: is the amount by which to rotate, in the range 0 to 31, encoded in the "imms" field.

For the 64-bit variant: is the amount by which to rotate, in the range 0 to 63, encoded in the "imms" field.

Operation

The description of EXTR gives the operational pseudocode for this instruction.

Operational information

If PSTATE.DIT is 1:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
Was this page helpful? Yes No