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7.1. New features for NEON and Floating-point in AArch64

AArch64 NEON is based upon the existing AArch32 NEON, with the following changes:

  • There are now thirty-two 128-bit registers, rather than the 16 available for ARMv7.

  • Smaller registers are no longer packed into larger registers, but are mapped one-to-one to the lower-order bits of the 128-bit register. A single precision floating-point value uses the lower 32 bits, while double precision value uses the lower 64 bits of the 128-bit register. See NEON and Floating-Point architecture.

  • The V prefix present in ARMv7-A NEON instructions has been removed.

  • Writes of 64 bits or less to a vector register result in the higher bits being zeroed.

  • In AArch64, there are no SIMD or saturating arithmetic instructions which operate on the general-purpose registers. Such operations use the NEON registers.

  • New lane insert and extract instructions have been added to support the new register packing scheme.

  • Additional instructions are provided for generating or consuming the top 64 bits of a 128-bit vector register. Data-processing instructions, which would generate more than one result register (widening to a 256-bit vector), or consume two sources (narrowing to a 128-bit vector), have been split into separate instructions.

  • A new set of vector reduction operations provide across-lane sum, minimum and maximum.

  • Some existing instructions have been extended to support 64-bit integer values. For example, comparison, addition, absolute value and negate, including saturating versions.

  • Saturating instructions have been extended to include Unsigned Accumulate into Signed, and Signed into Unsigned Accumulate.

  • Support is provided in AArch64 NEON for double-precision floating-point and full IEEE754 operation including rounding modes, denormalized numbers, and NaN handling.

Floating-point has been enhanced in AArch64 with the following changes:

  • The V prefix present in ARMv7-A floating-point instructions has been replaced with an F.

  • Support for both single-precision (32-bit) and double-precision (64-bit) floating-point vector data types and arithmetic as defined by the IEEE 754 floating-point standard, honoring the FPCR Rounding Mode field, the Default NaN control, the Flush-to-Zero control, and (where supported by the implementation) the Exception trap enable bits.

  • Load/Store addressing modes for FP/NEON registers are identical to integer Load/Stores, including the ability to Load or Store a pair of floating-point registers.

  • Floating-point FCSEL and Select and Compare instructions, equivalent to the integer CSEL and CCMP have been added.

    Floating-point FCMP, FCMPE, FCCMP, and FCCMP set the PSTATE.{N, Z, C, V} flags based on the result of the floating-point comparison and do not modify the condition flags in the Floating-Point Status Register (FPSR), as is the case in ARMv7.

  • All floating-point Multiply-Add and Multiply-Subtract instructions are fused.

    Fused multiply was introduced in VFPv4 and means that the result of the multiply is not rounded before being used in the addition. In earlier ARM floating-point architectures, a Multiply Accumulate operation would perform rounding of both the intermediate result and final results, which could potentially cause a small loss of precision.

  • Additional conversion operations are provided, for example, between 64-bit integer and floating-point and between half-precision and double-precision.

    Convert float to integer (FCVTxU, FCVTxS) instructions encode a directed rounding mode:

    • Towards zero.

    • Towards +∞.

    • Towards -∞.

    • Nearest with ties to even.

    • Nearest with ties to away.

  • Round float to nearest integer in floating-point format (FRINTx) has been added, with the same directed rounding modes, as well as rounding according to the ambient rounding mode.

  • A new double to single precision Down-Convert instruction with inexact rounding to odd, suitable for ongoing down-conversion to half-precision with correct rounding (FCVTXN).

  • FMINNM and FMAXNM instructions have been added which implement the IEEE754-2008 minNum() and maxNum() operations. These return the numerical value if one of the operands is a quiet NaN.

  • Instructions to accelerate floating-point vector normalization have been added (FRECPX, FMULX).

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