The ARMv8 architecture defines two mutually-exclusive memory types. All regions of memory are configured as one or the other of these two types, which are Normal and Device. A third memory type, Strongly Ordered, is part of the ARMv7 architecture. The differences between this type and Device memory are few and it is therefore now omitted in ARMv8. (See Device memory.)
In addition to the memory type, attributes also provide control over cacheability, shareability, access, and execution permissions. Shareable and cache properties pertain only to Normal memory. Device regions are always deemed to be non-cacheable and outer-shareable. For cacheable locations, you can use attributes to indicate cache allocation policy to the processor.
The memory type is not directly encoded in the translation table entry. Instead, each block entry specifies a 3-bit index into a table of memory types. This table is stored in the Memory Attribute Indirection Register MAIR_ELn. This table has eight entries and each of those entries has eight bits, as shown in Figure 13.1.
Although the translation table block entry itself does not
directly contain the memory type encoding, the TLB entry inside
the processor usually stores this information for a specific entry. Therefore,
changes to MAIR_ELn might not be observed until
after both an
ISB instruction barrier and a TLB invalidate