The Power State Coordination Interface (PSCI) provides an OS agnostic method for implementing power management use cases where cores can be powered up or down. This includes:
Core idle management.
Dynamic addition and removal of cores (hotplug), and secondary core boot.
System shutdown and reset.
The messages sent using this interface are received by all relevant levels of execution. That is, if EL2 and EL3 are implemented, a message sent by a Rich OS executing in a guest must be received by a hypervisor. If the hypervisor sends it, the message must be received by the secure firmware that then coordinates with a Trusted OS. This allows each operating system to determine whether context saving is required.
For more information, see the Power State Coordination Interface (PSCI) specification.