In addition to storing individual translations within the TLB, you can configure the MMU to store translation tables in cacheable memory. This usually provides much faster access to tables than always reading from external memory. TCR_EL1 has additional fields that control this.
The additional fields specify the cacheability and shareability of translation tables for TTBR0 and TTBR1. The relevant fields are called SH0/1 Shareability, IRGN0/1 Inner Cacheable, and ORGN0/1 Outer Cacheable. Table 12.2 shows the permitted settings for cacheability.
|IRGN/ORGN bits for TTBR0/TTBR1||Cacheable Property|
|00||Normal memory, Inner Non-cacheable|
|01||Normal memory, Inner Write-Back Write-Allocate Cacheable|
|10||Normal memory, Inner Write-Through Cacheable|
|11||Normal memory, Inner Write-Back no Write-Allocate Cacheable|
The corresponding table for shareability of memory is associated with translation table walks. For a device or strongly-ordered memory region, the value is ignored.
The attributes specified in the TCR_EL1 must be the same as those specified for the virtual memory region in which the translation tables are stored. Caching the translation tables is the normal default behavior.