The cache policies enable us to describe when a line should be allocated to the data cache and what should happen when a store instruction is executed that hits in the data cache.
The cache allocation policies are:
- Write allocation (WA)
A cache line is allocated on a write miss. This means that executing a store instruction on the processor might cause a burst read to occur. There is a linefill to obtain the data for the cache line, before the write is performed. The cache contains the whole line, which is its smallest loadable unit, even if you are only writing to a single byte within the line.
- Read allocation (RA)
A cache line is allocated on a read miss.
The cache update policies are:
- Write-back (WB)
- Write-through (WT)
Data reads which hit in the cache behave the same in both WT and WB cache modes.
The cacheable properties of normal memory are specified separately as inner and outer attributes. The divide between inner and outer is implementation defined and is covered in greater detail in Chapter 13. Typically, inner attributes are used by the integrated caches, and outer attributes are made available on the processor memory bus for use by external caches.
Normal memory can be speculatively accessed by the processor and this means that it can potentially automatically load data into the cache without the programmer having explicitly requested a specific address. This is covered in more detail in Chapter 13 Memory Ordering. However, it is also possible for the programmer to give an indication to the core about which data is used in the future. The ARMv8-A provides preload hint instructions. It is implementation defined whether the caches support speculation and preload. The following instructions are available:
PLDL1KEEP, [Xm, #imm]; This indicates a Prefetch for a load from Xm + offset into the L1 cache as a temporal prefetch, which means that the data might be used more than once.
Rm// Preload data from address in Rm to cache
More generally, the A64 instruction to prefetch memory has the following form:
PRFM <prfop>, addr
<type><target><policy> | #uimm5
PLDfor prefetch for load
PSTfor prefetch for store
L1for L1 cache,
L2for L2 cache,
L3for L3 cache
KEEPfor retain or temporal prefetch means allocate in cache normally
STRMfor streaming or non-temporal prefetch means the memory is used only once
Represents the hint encodings as a 5-bit immediate. These are optional.