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2. About the internal memory interface

The AXI internal memory interface, IntMemAxi, has the following features:

  • It provides a single-port memory interface configurable for synchronous SRAM or ROM.

  • The HDL code is supplied as Verilog.

  • The memory footprint is that of the connected SRAM or ROM.

  • It accepts a single address for each of the read and write channels.

  • It uses round-robin arbitration between read and write transactions, the default is read.

  • For write transactions, the first data transfer can take place 2 cycles after the address is accepted. Subsequent data transfers can complete in consecutive cycles.For read transactions:

    With one wait state

    The first data transfer can take place 2 cycles after the address is accepted. Subsequent data transfers can complete in consecutive cycles.

    With zero wait states

    The first data transfer can take place 3 cycles after the address is accepted. Subsequent data transfers take 2 cycles.

  • It supports:

    • all AMBA AXI channels except the low power channel

    • all AXI burst types

    • aligned and unaligned transfer types.

  • You can configure the following parameters:

    • data width of 64 bits or 32 bits

    • ID width

    • wait states, single or none, for SRAM and ROM reads

    • whether the interface is to be used with SRAM or ROM

    • memory read access to be zero or one wait-state

    • MEM_ADDR_WIDTH, MEM_INIT_FILE_0, and MEM_INIT_FILE_1 for IntMemBhavAxi.

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