The interface conforms to the following timing guidelines:
AXI inputs must be valid for 30% of the cycle before the rising edge of CLK and outputs must become valid within 20% of cycle after the rising edge of CLK.
Timing characteristics are confirmed by performing synthesis on the block using the slow-slow process point of the Artisan SAGE HS library for the TSMC CL013G process at a target speed of 200MHz.
The signals on the memory port of the interface conform to the timing requirements required by the single ported synchronous memory component produced by RAM Compiler for the TSMC CL013G process technology with the following compiled features:
8-bit mask write.