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1.2. Functional description

The AXI to ARM11 AHB-Lite bridge has the following features:

  • It translates AXI transactions to AHB-Lite bursts with the following restrictions:

    • exclusive accesses are available by using the bridge and an external exclusive access monitor

    • unaligned and sparse accesses are available by using the AXI ARM11 AHB-Lite bridge together with an ARM11-capable AHB interconnect, or an external byte lane strobe converter.

  • The bridge only supports one outstanding transaction at any one time on each address channel. Interface attributes describes this.

  • Initiation of AHB write bursts are related to AXI address and write channel transfers:

    there is a minimum latency of two clock cycles from the acceptance of an AXI transaction, AWVALID or ARVALID asserted, to the start of the AHB transaction when HTRANS is driven to NONSEQ

    • the first data transfer in a write burst waits for the AXI address, AWVALID, and the first AXI write transfer, WVALID

    • subsequent data transfers in a write burst wait for the AXI write transfer, WVALID, and busy cycles are issued on the AHB domain until the data arrives

    • the AXI write response is issued on the completion of the final write data data transfer of the burst.

  • Initiation of AHB read bursts are related to AXI address and read channel transfers:

    • the first AHB address is issued on or after the arrival of the AXI address transfer, ARVALID

    • subsequent AHB transfers wait for the acceptance of the read data by the AXI read channel, RREADY, and busy cycles are issued on the AHB domain until the data has been accepted.

  • Only the OKAY, EXOKAY and SLVERR responses are generated:

    • an error response returned on any data transfer of an AHB write burst causes a write response of SLVERR

    • read responses are translated on a per transfer basis

    • an AHB XFAIL response results in an AXI OKAY response and an AHB OKAY response to an exclusive access results in an AXI EXOKAY response.

  • All AXI transactions are mapped, where possible, to an equivalent AHB burst:

    • wrapping and incrementing bursts of length 4, 8, and 16 are converted into the equivalent length AHB bursts

    • incrementing bursts of length 1, wrapping bursts of length 2, and all fixed address transactions are converted to sequences of AHB SINGLE bursts

    • any burst that crosses a 1KB address boundary is converted into INCR bursts with the burst restarted, HTRANS is overridden to NONSEQ, when the boundary is crossed

    • all remaining incrementing and wrapping bursts are converted into AHB INCR bursts.

  • AXI xUSER sideband signals are mapped onto additional AHB domain sideband signals:

    • AXI ARUSER and AWUSER, as appropriate, are used for HAUSER, an address phase signal

    • AXI WUSER is used for HWUSER, a data phase signal

    • a data phase HRUSER signal is used for the AXI RUSER signal

    • the AXI BUSER signal is unused.

    You can parametrize the width of the address phase signals and data phase signals between 1 and 32.

  • The address transfer ID is used for read and write transfers:

    • ARID is used for the associated RID, and for HMASTER during AHB read transfers

    • AWID is used for the associated BID, and for HMASTER during AHB write transfers.

  • HDL code is supplied as Verilog.

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