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4.3. Register descriptions

This section provides descriptions of the registers listed in Table 2.

Note

Three TZPC Decode Protection Status Registers, Decode Protection Set Registers, and Decode Protection Clear Registers are implemented to derive the associated signals, TZPCDECPROT0, TZPCDECPROT1, and TZPCDECPROT2. The descriptions in this section use the letter x to denote an individual register number of 0-2.

Secure RAM Region Size Register

The read and write TZPCR0SIZE Register has a reset value of 0x00000200. It sets the size of the secure region in the internal RAM. Figure 3 shows the register bit assignments.

Figure 3. TZPCR0SIZE Register bit assignments

TZPCR0SIZE Register bit assignments

Table 3 lists the register bit assignments.

TZPCR0SIZE Register bit assignments
BitsNameFunction
[31:10]-Read undefined. Write as zero.
[9:0]R0SIZE

Secure RAM region size in 4KB steps:

0x00000000 = no secure region

0x00000001 = 4KB secure region

0x00000002 = 8KB secure region

0x000001FF = 2044KB secure region.

0x00000200 or above sets the entire RAM to secure regardless of size

Decode Protection 0-2 Status Registers

The read-only TZPCDECPROTxStat Registers have a reset value of 0x00000000. They provide the status of the appropriate decode protection 0-3 output signals. Figure 4 shows the register bit assignments.

Figure 4. TZPCDECPROTxStat Register bit assignments

TZPCDECPROTxStat Register bit assignments

Table 4 lists the register bit assignments.

TZPCDECPROTxStat Register bit assignments
BitsNameFunction
[31:8]-Read undefined.
[7:0]DECPROTxStat

Shows the status of the decode protection output:

0 = decode region corresponding to the bit is secure

1 = decode region corresponding to the bit is non-secure.

There is one bit of the register for each protection output, eight outputs are implemented as standard.

Decode Protection 0-2 Set Registers

The write-only TZPCDECPROTxSet Registers set the appropriate bits in the TZPCDECPROTx[7:0] output signals. Figure 5 shows the register bit assignments.

Figure 5. TZPCDECPROTxSet Register bit assignments

TZPCDECPROTxSet Register bit assignments

Table 5 lists the register bit assignments.

TZPCDECPROTxSet Register bit assignments
BitsNameFunction
[31:8]-Write as zero.
[7:0]DECPROTxSet

Sets the corresponding decode protection output:

0 = no effect

1 = set decode region to non-secure.

There is one bit of the register for each protection output, eight outputs are implemented as standard.

Decode Protection 0-2 Clear Registers

The write-only TZPCDECPROTxClr Registers clear the appropriate bits in the TZPCDECPROTx[7:0] output signals. Figure 6 shows the register bit assignments.

Figure 6. TZPCDECPROT0Clr Register bit assignments

TZPCDECPROT0Clr Register bit assignments

Table 6 lists the register bit assignments.

TZPCDECPROTxClr Register bit assignments
BitsNameFunction
[31:8]-Write as zero.
[7:0]DECPROTxClr

Clears the corresponding decode protection output:

0 = no effect

1 = set decode region to secure.

There is one bit of the register for each protection output, eight outputs are implemented as standard.

TZPC Peripheral Identification Registers 0-3

The read-only TZPCPERIPHID0-3 Registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. Figure 7 shows how you can treat the registers conceptually as a single 32-bit register. The registers provide the following options for the peripheral:

Part number [11:0]

This identifies the peripheral. The three digit product code 0x870 is used for the TZPC.

Designer [19:12]

This is the identification of the designer. ARM Limited is 0x41, ASCII A.

Revision number [23:20]

This is the revision number of the peripheral. The revision number starts from 0 and the value is revision-dependent.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 7. Peripheral identification Register bit assignments

Peripheral identification Register bit assignments

The four 8-bit peripheral identification registers are described in:

Peripheral Identification Register 0

The read-only TZPCPERIPHID0 Register is hard-coded and the fields in the register determine the reset value. Table 7 lists the register bit assignments.

TZPCPERIPHID0 Register bit assignments
BitsNameFunction
[31:8]-Read undefined
[7:0]Partnumber0These bits read back as 0x70
Peripheral Identification Register 1

The read-only TZPCPERIPHID1 Register is hard-coded and the fields in the register determine the reset value. Table 8 lists the register bit assignments.

TZPCPERIPHID1 Register bit assignments
BitsNameFunction
[31:8]-Read undefined.
[7:4]Designer0These bits read back as 0x1
[3:0]Partnumber1These bits read back as 0x8
Peripheral Identification Register 2

The read-only TZPCPERIPHID2 Register is hard-coded and the fields in the register determine the reset value. Table 9 lists the register bit assignments.

TZPCPERIPHID2 Register bit assignments
BitsNameFunction
[31:8]-Read undefined
[7:4]RevisionThese bits read back as the revision number which can be 0-15
[3:0]Designer1These bits read back as 0x4
Peripheral Identification Register 3

The read-only TZPCPERIPHID3 Register is hard-coded and the fields in the register determine the reset value. Table 10 lists the register bit assignments.

TZPCPERIPHID3 Register bit assignments
BitsNameFunction
[31:8]-Read undefined
[7:0]ConfigurationThese bits read back as 0x00

Identification Registers 0-3

The read-only TZPCPCELLID0-3 Registers are four 8-bit registers that span address locations 0xFF0-0xFFC. You can treat the register conceptually as a single 32-bit register. The register is used for a standard cross-peripheral identification system. Figure 8 shows the register bit assignments.

Figure 8. TZPC Identification Register bit assignments

TZPC Identification Register bit assignments

The four 8-bit TZPC Identification Registers are described in:

TZPC Identification Register 0

The read-only TZPCPCELLID0 Register is hard-coded and the fields in the register determine the reset value. Table 11 lists the register bit assignments

TZPCPCELLID0 Register bit assignments
BitsNameFunction
[31:8]-Read undefined
[7:0]TZPCPCELLID0These bits read back as 0x0D
TZPC Identification Register 1

The read-only TZPCPCELLID1 Register is hard-coded and the fields in the register determine the reset value. Table 12 lists the register bit assignments.

TZPCPCELLID1 Register bit assignments
BitsNameFunction
[31:8]-Read undefined
[7:0]TZPCPCELLID1These bits read back as 0xF0
TZPC Identification Register 2

The read-only TZPCPCELLID2 Register is hard-coded and the fields in the register determine the reset value. Table 13 lists the register bit assignments.

TZPCPCELLID2 Register bit assignments
BitsNameFunction
[31:8]-Read undefined
[7:0]TZPCPCELLID2These bits read back as 0x05
TZPC Identification Register 3

The read-only TZPCPCELLID3 Register is hard-coded and the fields in the register determine the reset value. Table 14 lists the register bit assignments.

TZPCPCELLID3 Register bit assignments
BitsNameFunction
[31:8]-Read undefined
[7:0]TZPCPCELLID3These bits read back as 0x00
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