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2. About the AXI downsizer

DownsizerAxi is an AXI infrastructure component that enables you to connect a 64-bit AXI bus to a 32-bit AXI bus. It converts 64-bit AXI transactions into appropriate 32-bit transactions, and handles the multiplexing of the data channels.

The AXI downsizer has the following features:

  • Implements a 64-bit data-width AXI slave port and a 32-bit AXI master port.

  • Address transfers of 8, 16, and 32-bit pass through unchanged. The associated data transfers are multiplexed onto the correct byte lanes on each port.

  • The latency of DownsizerAXI is as follows:

    • AxVALIDS to AxVALIDM, one clock cycle[1]

    • ARVALIDS to RVALIDS, two clock cycles in pass-through mode, and three clock cycles in downsize mode[2]

    • AWVALIDS to WVALIDM, two clock cycles[2], [3].

  • Each data channel, read and write, includes buffering for two active transactions, that enables the address translation latency to be isolated from the maximum data bandwidth for transactions with lengths greater than 1.

  • 64-bit transactions are modified as follows:

    • AxSIZE is changed to indicate 32-bit[1]

    • any WRAP or INCR burst of length eight or less is doubled in length, AxLEN changed[1]

    • any INCR burst of length nine or more is split into two transactions, AxLEN copied[1]

    • any 16-word aligned WRAP burst of length 16 is split into two INCR transactions

    • any WRAP burst of length 16 that is not 16-word aligned is split into three INCR transactions

    • any FIXED burst is split into a number of transactions equal to the length of the FIXED burst. Each of the transactions generated is a length 2 INCR burst, unless the original FIXED burst is unaligned, then the length is 1.

  • For locked sequences, if the terminating unlocked transfer is 64-bit, and results in multiple 32-bit transactions, then all 32-bit transactions except the ultimate one are locked.

  • 64-bit exclusive accesses are supported except for transactions that would result in two or more 32-bit transactions. The AXI protocol defines that only a single outstanding exclusive transaction is permitted.

[1] x can be either R or W.

[2] This applies to the first data transfer of the transaction.

[3] This assumes that WVALID for the first write data transfer is asserted when AWVALID is asserted.

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