The AXI upwards-synchronizing bridge,
enables a slow AXI clock domain to communicate with a faster one
using a common clock select. Figure 1 shows
in a system where an AXI master is running at 100MHz and an AXI slave
is running at 200MHz.
SyncUpAxi 1:n bridge has the following
1:n clock synchronizing using a common clock select input where n >= 1
CSYSREQ, CSYSACK, and CACTIVE are synchronized on the low-power interface
synchronizes the channel flow control signals on the AXI interface:
Write address channel.
Write data channel.
Write response channel.
Read address channel.
Read data channel.
only the handshake signals are synchronized on the write response, and read data channels
buffered synchronization of the write address, write data, and read address channels
maximum latency of one clock period in the slow clock domain
the HDL code is supplied as Verilog.