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4.1. AC characteristics

The upwards-synchronizing bridge adheres to the following timing guidelines. The figures relate to the percentage of clock cycle permitted for each function:

  • inputs to registers must be valid for 40% prior to the rising edge of the fast clock

  • outputs from registers must be valid for 20% after the rising edge of the fast clock

  • combinatorial paths must not take longer than 10% of the complete fast clock cycle.

Note

There are combinatorial paths from ACLKSEL to:

  • AWVALIDM

  • ARVALIDM

  • WVALIDM

  • BREADYM

  • RREADYM.

The delay on these paths is a maximum of 10% of the clock cycle.

Note

If the component is used only for clock ratios greater than 1:1, you can relax these constraints accordingly.

Timing characteristics are confirmed by performing synthesis on the block using the slow-slow process point of the Artisan SAGE HS library for the TSMC CL013G process at a target speed of 200MHz.

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