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2. About the AXI upwards-synchronizing bridge

The AXI upwards-synchronizing bridge, SyncUpAxi, enables a slow AXI clock domain to communicate with a faster one using a common clock select. Figure 1 shows SyncUpAxi used in a system where an AXI master is running at 100MHz and an AXI slave is running at 200MHz.

Figure 1. upwards-synchronizing bridge block diagram

Figure 1. upwards-synchronizing bridge block
diagram

The SyncUpAxi 1:n bridge has the following features:

  • 1:n clock synchronizing using a common clock select input where n >= 1

  • CSYSREQ, CSYSACK, and CACTIVE are synchronized on the low-power interface

  • synchronizes the channel flow control signals on the AXI interface:

    AW

    Write address channel.

    W

    Write data channel.

    B

    Write response channel.

    AR

    Read address channel.

    R

    Read data channel.

  • only the handshake signals are synchronized on the write response, and read data channels

  • buffered synchronization of the write address, write data, and read address channels

  • maximum latency of one clock period in the slow clock domain

  • the HDL code is supplied as Verilog.

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