The AXI asynchronous bridge,
enables two AXI clock domains to communicate. Figure 1 shows
data being transferred between two AXI clock domains.
The bridge provides buffered synchronization of the AXI channels:
Write address channel.
Write data channel.
Write response channel.
Read address channel.
Read data channel.
The HDL code is supplied as Verilog.
The major features of the bridge are:
single independent AXI master and AXI slave interfaces
all AXI channels are buffered independently
configurable FIFO buffer depth for each AXI channel
dynamic synchronous bypass mode.
The PrimeCell Infrastructure AMBA 3 AXI Asynchronous Bridge (BP132) Design Manual provides more information about these features.