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3.1. Operation

At the top level, the bridge comprises:

  • five FIFOs, one for each AXI channel

  • logic to manage transition to and from synchronous bypass mode.

There is no requirement for the bridge to examine any part of the data in an AXI channel, it can therefore be treated as unstructured and consider each channel as valid, ready, and payload data.

Figure 2 shows a block diagram of the major internal component blocks. The clock, reset, and scan pins are omitted for clarity.

Figure 2. Asynchronous bridge components

Figure 2. Asynchronous bridge components

Each channel FIFO is divided into two halves that correspond to the source of the clock for the components in them.

ACLKS

Connects to the following:

  • write address channel FIFO write half

  • write data channel FIFO write half

  • read address channel FIFO write half

  • write response channel FIFO read half

  • read data channel FIFO read half.

ACLKM

Connects to the following:

  • write address channel FIFO read half

  • write data channel FIFO read half

  • read address channel FIFO read half

  • write response channel FIFO write half

  • read data channel FIFO write half.

Two of the FIFOs operate in the opposite direction to the other three but all five behave in the same way with respect to their read and write halves.

The PrimeCell Infrastructure AMBA 3 AXI Asynchronous Bridge (BP132) Design Manual provides more information about the FIFOs.

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