The asynchronous bridge adheres to the following timing guidelines. The figures relate to the percentage of clock cycle permitted for each function:
AXI inputs must be valid for 40% prior to the rising edge of the clock.
AXI outputs shall be valid by 20% after the rising edge of the clock.
Combinatorial paths occupy no more than 9% of the clock cycle. There are no combinatorial through paths in the bridge except when it is in synchronous bypass mode. The multiplexing and demultiplexing of the signals from one side of the bridge to the other in synchronous bypass mode is synthesized as a combinatorial path.
Performing synthesis on the block using the slow-slow process point of the Artisan SAGE HS library for the TSMC CL013G process, at a target speed of 200MHz, confirms the timing characteristics.