This section gives some example transfer sequences for the BusMatrix. For clarity, all transfer sequences shown are read operations, but the same cycle behavior occurs for writes.
Figure 8 shows simultaneous access from both ports with switching occurring every transfer. In this example, the shared slave inserts a wait state on the first transfer from each port, but all subsequent transfers are zero wait state.
Figure 9 shows a port accessing the shared slave when the other input port is idle. At the start of the sequence, a single wait state is inserted by the BusMatrix. This example shows the shared slave inserting one wait state for each of the first two accesses.