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6.5. CM interrupt control

Figure 6.9 shows the architecture of the interrupt control system on the CM922T-XA10 core module fitted to an Integrator/AP motherboard. It shows the routing of the IRQ signals but omits the FIQ signals because they are routed in a similar way.

Figure 6.9. CM image interrupt control (showing IRQs only)

Figure 6.9. CM image interrupt control (showing
IRQs only)

Note

The interrupt signals IRQ[3:1] and FIQ[3:1] on the core module are routed to the PLD but are unused by the CM image.

The Excalibur chip contains an interrupt controller within the stripe, which is present whether or not the PLD section is programmed. The CM image instantiates a second debug interrupt controller into the PLD that controls the COMMTx and COMMRx interrupts for the core.

The System controller FPGA on the AP also contains IRQ and FIQ interrupt controllers. These control interrupts from the logic module connector (EXPB), from internal peripherals, and from the PCI (not shown). Each interrupt source can be assigned to the IRQ or FIQ input to any of up to four processors. For more information about the interrupt controller on the AP, see the Integrator/AP User Guide.

The assignment of the interrupts from the AP and from the debug interrupt controller to the stripe controller inputs are shown in Table 6.11.

CM image interrupt assignment
PLD_INTCM
0CM_FIQ
1nFIQ0
2CM_IRQ
3nIRQ0
4-
5-
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