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7.11. Integrator/CP922T interrupt control

Figure 7.13 shows the interrupt control architecture for the Integrator/CP922T system. The CP image contains three interrupt controllers. Their use is described in:

Figure 7.13. Interrupt architecture (CP image)

Figure 7.13. Interrupt architecture (CP image)

Integrator/CP system interrupts are generated by the Primary Interrupt Controller (PIC), the Secondary Interrupt Controller (SIC), and the CM Interrupt Controller (CIC). The PIC interrupts are connected to the interrupt controller within the stripe and are assigned to the INT_PLD[3:0] signals as shown in Table 7.14.

CP image interrupt assignment
INT_PLDCP
0CM_FIQ
1CP_FIQ
2CM_IRQ
3CP_IRQ
4-
5-

Detecting and clearing interrupts requires that each interrupt controller be correctly initialized as well as the interrupt control register in the individual peripheral.

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