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4.6.3. Clock programming interface

The ICS307 is a serially programmed device. It provides a control interface comprising three signals:

CLKDATA

This signal is used to pass the control parameters as a 24-bit word into a shift register within the ICS307. This signal is common to both chips.

SCLKn

This signal is used to clock the control parameter bits into the shift register. Each bit is transferred in 1 clock cycle.

CLKnSTRB

This is a strobe signal that is asserted after the 24th bit of the parameter word has been transferred into the shift register. It causes the data to be transferred into the internal registers of the ICS307.

Figure 4.12 shows the timing for the serial programming interface signals.

Figure 4.12. Clock generator control interface timing

Figure 4.12. Clock generator control interface
timing

The control parameters are transferred using the 24-bit control word shown in Figure 4.13.

Figure 4.13. Clock control word

Figure 4.13. Clock control word

The control parameters are as follows:

C[1:0]

Internal load capacitance for the crystal. Always set this to 00.

TTL

Duty cycle setting. Always set this to 1.

F[1:0]

Function setting for CLK2:

  • 00 selects CLK2=Ref (this is the default)

  • 01 selects CLK2=Ref/2

  • 10 selects CLK2 = OFF (LOW).

  • 11 selects CLK2=CLK1/2.

Note

The C, TTL, and F parameters are set to the default values at reset and are normally not modifiable. For the basic example image however, these values are programmable, see Basic example oscillator divisor registers.

S[2:0]

OD selection:

  • 000 = divide by 10

  • 001 = divide by 2

  • 010 = divide by 8

  • 011 = divide by 4

  • 100 = divide by 5

  • 101 = divide by 7

  • 110 = divide by 3

  • 111 = divide by 6.

V[8:0]

VDW.

R[6:0]

RDW.

The configuration images provide registers that you can use to program some or all of these parameters, and each provides a functional block to manage the transfer of the parameters into the ICS307s.

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