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4.8. Interrupt architecture

The stripe provides an interrupt controller that takes interrupt requests from devices within the stripe and six interrupt request lines assigned to the PLD. This is shown in Figure 4.15.

Figure 4.15. Interrupt control

Figure 4.15. Interrupt control

Interrupt request signals from other Integrator modules are routed onto the PLD interrupt requests INT_PLD[5:0] by functional blocks implemented in the PLD.

For example, the Integrator/AP provides an interrupt controller within the system controller FPGA, and requests from this are routed to the PLD using the nFIQ[3:0] and nIRQ[3:0] signal pins on the HDRA connector. The CM image routes nIRQ[0] and nFIQ[0] onto the INT_PLD[3] and INT_PLD[1] signals as shown in Table 4.10.

Assignment of interrupts for the PLD images

Table 4.10 shows how the CM, CP, and IM-PD1 images supplied with the core module assign interrupt requests to the INT_PLD[5:0] signals, and Table 4.11 describes the interrupt request signals.

Interrupt sources
nFIQ[0]These interrupt requests are generated on the Integrator/AP and routed to the core module PLD using the HDRA or EXPA connectors. The interrupt controller for these is instantiated into the system controller FPGA on the Integrator/AP motherboard. See the Integrator/AP User Guide.
CM_FIQThese interrupt requests are from the CM interrupt controller instantiated into the core module PLD. Requests are generated by the COMMRx and COMMTx interrupts. See CM interrupt control.CM interrupt control
CP_FIQThese interrupt requests are from the Primary Interrupt Controller (PIC) instantiated into the core module PLD in the CP image. See Integrator/CP922T interrupt control.
VIC_FIQThese interrupt requests are the Vectored Interrupt Controller (VIC) instantiated into the core module PLD by the IM-PD1 image. See Integrator/CM922T-XA10 and IM-PD1 interrupt control.
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