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4.7.1. Reset sequence

Resetting the core module causes any other Integrator modules to which it is attached to be reset. The reset control logic instantiated into the PLD and any other programmable devices on other Integrator modules coordinate the reset sequence to ensure that the system is initialized in a predictable and reliable way.

The reset sequence for the core module is as follows:

  1. When the core module is powered on the signal nPORESET is asserted and held for 100ms by the POR circuit. The delay before releasing nPORESET ensures that power supplies are stable before PLD configuration begins.

    Assertion of the nPORESET signal resets the core and stripe components, causing the PLD configuration to be reloaded.

  2. For subsequent resets, the PLD detects the assertion of one of the other reset signal sources and asserts nRESETOUT and nSRST. The nSRST is used to trigger a reset of other modules in the system.

    The nRESETOUT signal is used to assert nPORESET. The POR delay circuit is used to ensure that the previous PLD configuration is cleared and that the reset sequence completes reliably.

  3. When PLD configuration is complete, the PLD asserts INIT_DONE and illuminates the DONE LED.

  4. A delayed version of INIT_DONE signal, called DONE_IN, is fed back into the PLD to assert DONE_OUT. This signal is used to control the state of the GLB_DONE signal.

  5. The GLB_DONE signal is an open drain signal shared by the Excalibur PLD and FPGAs on other Integrator modules. Each module monitors and controls GLB_DONE. It goes HIGH only when all the programmable devices have been configured. This ensures that the release of nSRST by all of the modules is properly coordinated.

    All Integrator modules with programmable logic provide an LED to give a visual indication that they have completed their configuration sequence. See the user guide for your Integrator module.

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