Table 4.9 describes the reset signals.
|nPORESET||Power-ON reset||Input||This reset is asserted when the system is powered ON or when the nRESETOUT signal is asserted by the reset controller in the PLD. It resets the ARM core and stripe logic and causes the PLD configuration to be reloaded.|
This signal triggers a full reset of the PLD and stripe by asserting the nPORESEST input to the stripe. It is generated when any of the reset sources (for example, nPBRESET) or software reset is asserted.
The PBRESET signal is generated by pressing the reset button on the core module.
As an output the nSRST signal is driven LOW by the core module PLD when any reset source (for example, nPBRESET) or software reset is asserted.
As an input, nSRST can be driven LOW by Multi-ICE or by another module connected to the HDRB connector.
As an output, nSYSRST is generated by the PLD if the core module is used standalone or with an Integrator/CP baseboard.
As an input if the core module is used with an Integrator/AP motherboard, nSYSRST is generated by the system controller FPGA on the motherboard.
|PLD configuration complete|
This signal is generated by the PLD to indicate that the configuration process is complete.
This signal is routed round the system through the HDRB connectors to all FPGAs and large PLDs in the system.
The system is held in reset until GLB_DONE is driven HIGH.