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4.7.2. Reset signals

Table 4.9 describes the reset signals.

Name

Description

Type

Function

nPORESETPower-ON resetInputThis reset is asserted when the system is powered ON or when the nRESETOUT signal is asserted by the reset controller in the PLD. It resets the ARM core and stripe logic and causes the PLD configuration to be reloaded.

nRESETOUT

System reset

Output

This signal triggers a full reset of the PLD and stripe by asserting the nPORESEST input to the stripe. It is generated when any of the reset sources (for example, nPBRESET) or software reset is asserted.

nPBRESET

Push-button reset

Input

The PBRESET signal is generated by pressing the reset button on the core module.

nSRST

System reset

Output

As an output the nSRST signal is driven LOW by the core module PLD when any reset source (for example, nPBRESET) or software reset is asserted.

Input

As an input, nSRST can be driven LOW by Multi-ICE or by another module connected to the HDRB connector.

nSYSRST

System reset

Output

As an output, nSYSRST is generated by the PLD if the core module is used standalone or with an Integrator/CP baseboard.

Input

As an input if the core module is used with an Integrator/AP motherboard, nSYSRST is generated by the system controller FPGA on the motherboard.

INIT_DONE

PLD configuration complete

Output

This signal is generated by the PLD to indicate that the configuration process is complete.

GLB_DONE

PLD/FPGA configured

Open drain

This signal is routed round the system through the HDRB connectors to all FPGAs and large PLDs in the system.

The system is held in reset until GLB_DONE is driven HIGH.

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