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3.5.1. Synthesis

The synthesis stage of the tool flow takes the HDL files (either VHDL, Verilog, or a combination) and compiles them into a netlist targeted at a particular technology. For this core module, the target technology is Altera Excalibur. There are several synthesis tools available for both Windows and UNIX platforms, that provide support for a variety of programmable logic vendors. Synthesis information is supplied either through a GUI front end or command-line script. The information typically includes:

  • a list of HDL files

  • the target technology

  • required optimization, such as area or delay

  • timing and frequency requirements.

Refer to the documentation for your particular software tool for further information.

Common netlist file formats produced by synthesis are VQM and EDIF files (for example, filename.vqm). The netlist file is used by the next stage of the tool flow, which is place and route.