You copied the Doc URL to your clipboard.

3.4. Clock architecture

The Logic Tile has three on-board programmable clock generators that can provide clock sources for the FPGA. The tile can also accept clocks from the system.

Clock signals can be distributed to the tiles above and below and the tile can accept various clock signals from the tiles stacked above and below it. There is also provision for an external clock signal to be input to the tile using an SMA, SMB, or SMC connector (not fitted). Figure 3.3 shows the architecture of the clock system.

Figure 3.3. Clock signal overview

Clock signal overview

If multiple tiles are used in a stack, each tile can receive or generate clock signals. There are three basic systems for clocking multiple tiles from one clock source:

Global

A single clock line connects to all tiles. One tile generates the clock and the other tiles accept the clock. The phase of the clock is skewed between the different tiles because of differences in path length. (See Global clock.)

Retimed

One tile generates a differential (or two single-ended) clock signal. The tiles above and below retime a locally generated clock so that it has the same phase as the clock signal on the generating board. The skew of the incoming clock signal can be removed by a Delay Locked Loop (DLL) in the tile FPGA. (See Retimed clocks on multiple tiles.)

Delay-matched

A single clock line is generated on one tile and connected to two tiles above and below it in the stack. A delay matched version of the generated clock is input to the FPGA on the tile generating the clock. The trace paths for the five clocks are matched so that all five signals have the same phase when they reach the tile FPGAs. (See Delay-matched clock distribution (2 up/2 down).)

Details of the various clock signals and the clock generators are given in:

Was this page helpful? Yes No