The Logic Tile is fitted with a Xilinx Virtex II FPGA. The assignment of the input/output banks and JTAG implementation are described in the following sections:
For information about how the FPGA data is loaded, see Chapter 4 Configuring the FPGA and PLD.
For information about the configurations supplied with your Logic Tile, see the CD.
At power-up the FPGA loads its configuration data from a flash memory device. Parallel data from the flash is streamed by the PLD into the configuration port of the FPGA (see PLD). It is also possible to load an image directly into the FPGA through the JTAG connector, but the image is lost when power is turned off.
Figure 3.1 is a simplified view of the tile and illustrates the function of the FPGA and shows how it connects to the other devices in the Logic Tile. (Configuration devices are not shown.)