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3.2. Header signals

This section gives an overview of the signals present on the header connectors. See About the LT-XC2V4000+ Logic Tile for details of the board layout.

There are three headers on the top and bottom of the tile. The HDRX and HDRY headers are 180-way and the HDRZ connectors are 300-way. Signals on the upper headers are generally identified by a U (for example, YU143), while signals on the lower headers are generally identified by an L (for example XL179). Signals that go through both headers, however, do not use the U and L identification. Figure 3.2 shows a simplified view of the header signal routing (clock, control, and JTAG signals on HDRZ are not shown).


There is no correspondence between the header pin numbers and the signal numbers. For example, HDRY has signal YU113 on pin 48 of the upper connector.

For the signals on the upper and lower pins:

  • Some upper and lower pins are connected together and pass through signals that are not connected to any devices on the tile (for example the CLK_UP_THRU signal on pin 142 of lower HDRZ and pin 138 of upper HDRZ).

  • Some upper and lower pins are connected together but are also connected to devices on the tile (for example the CLK_GLOBAL signal on pin 150 of the upper and lower Z header is connects to a buffer).

  • Some upper and lower pins are only connected to the FPGA (for example YU[143:36] and YL[143:0]). The FPGA can be programmed to pass a modified version of the input signal on one pin to an output signal on a pin on the other side of the board, or the FPGA can treat the signals as completely independent.

  • Some pins on the lower connector can be connected to signals that are normally only available on the upper connector (See Foldover).

The header locations and pin numbering are shown in Header connectors.

The FPGA can be damaged if several pins configured as outputs (on connected Logic Tiles or motherboards) are connected and output a different logic levels.

Also, the signal input and output levels for many of the FPGA signals can be determined by an attached tile (see Variable I/O levels).

Figure 3.2. Simplified view of fold and through signals

Simplified view of fold and through signals
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