The Logic Tile does not have a JTAG connector. Use the connector on the baseboard or interface board:
For the Versatile/PB926EJ-S, the JTAG signals for the Logic Tile are routed through the headers to the tile at the top of the stack and from there back down through the tile. Use the JTAG or USB debug connector on the Versatile/PB926EJ-S.
If multiple RealView Logic Tiles are stacked on a Versatile/PB926EJ-S, the JTAG equipment is always connected to the Versatile/PB926EJ-S and the signals are routed upwards to the top tile and then back down to the Versatile/PB926EJ-S.
For use standalone or with an Integrator product, the Integrator/IM-LT1 Interface Module provides the JTAG connector for accessing the Logic Tile. See the Integrator/IM-LT1 Interface Module User Guide for more information on using JTAG and Multi-ICE.
There are two separate JTAG paths through the Logic Tile:
One path is for the configuration of programmable devices (FPGA, PLD, and flash memory). These JTAG signals are identified by the C_ prefix.
One path used in debug mode, connects to a TAP controller if one has been synthesized into the FPGA. These JTAG signals are identified by the D_ prefix.
The JTAG path chosen depends on whether the system is in configuration mode or debug mode. The CONFIG link on the baseboard or Interface Module controls the nCFGEN signal that is routed through the Interface Module and Logic Tile connectors.
The nCFGEN signal selects between the following modes:
Install the CONFIG link to use configuration mode for in-system reprogramming of the FPGAs, flash memory, or PLDs in the system.
If an Interface Module connects to a motherboard, such as the Integrator/AP, the motherboard is also set into config mode.
A manual configuration file (included on the CD supplied with the tile) must be used to configure Multi-ICE. The configuration file sets the JTAG TCK speed to 1MHz to ensure reliable operation (see also the Multi-ICE User Guide).
Remove the CONFIG link on the baseboard or Interface Module for debug mode. If the Logic Tile contains a virtual TAP controller it is placed in the debug JTAG path.
If the Logic Tile and Interface Module are mounted on an Integrator motherboard, the JTAG signals are routed from the Interface Module down to the motherboard and back up to the Interface Module and then up to the stacked Logic Tiles.
If the Logic Tile is mounted on a Versatile/PB926EJ-S, the JTAG signals are routed from the baseboard up to the stacked Logic Tiles.
Figure 3.16 shows the JTAG data signal routing for an Integrator system. (The config link is closed, so the figure shows a system in config mode.) Figure 3.17 shows the JTAG clock routing, and Figure 3.18 shows the JTAG TMS routing. Pullup resistors are not shown on the drawings.
In debug mode, the JTAG signals from the Interface Module are connected to FPGA input/output pins and enable you to implement a virtual TAP controller. This facility is provided for FPGA designs that require a TAP controller, for example, designs that include a synthesized processor.
If your design (or any other tile in the same stack) does not implement a TAP controller, then you must route TDI to TDO and TCK to RTCK.