The PLD implements a bytestreamer design that loads an image from configuration flash into the FPGA at power-up (when in debug mode). The PLD itself is preloaded with a nonvolatile image.
The GLOBAL_DONE signal indicates that every FPGA in the system has finished configuring. The system is held in reset until this signal goes HIGH. The PLD holds the GLOBAL_DONE signal low for 64 clock cycles after the LOCAL_DONE signal indicates that the FPGA has been configured. The PLD also provides the nRTCKEN signal to the motherboard and the signals to control the pass-through and foldover switches. The values for these signals are loaded serially from the FPGA after configuration has finished. If you are not using the example design, you must include the example HDL design to perform the serial transfer at startup.
Do not load the PLD with any image other than that supplied on the CD that accompanies the tile. Loading an incorrect image might render the board unusable. If the image in the PLD has been accidently erased, reload the image into the PLD by inserting the CONFIG link on the Interface Module and using the Progcards utility.