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3.8. Test points

The test points listed in Table 3.7 enable you to measure clock frequencies and FPGA core temperature.

Test points
Test PointSignalDescription
TP1CLK_GLOBAL_INBuffered version of global clock signal. This is fed to a GCLK input of the FPGA.
TP2CLK_GLOBAL_OUTBuffered version of global clock signal from the FPGA. (This signal is driven even if CLK_GLOBAL_OUT is disabled.)
TP3CLK_24MHZBuffered replica of the fixed-frequency reference clock signal that feeds CLK_24MHZ_FPGA and CLK_24MHZ_PLD.
TP8CLK_OUT

Buffered version of clock signal CLK_OUT_TO_BUF that drives the buffers for the dual/differential clocking scheme:

  • CLK_OUT_PLUS1

  • CLK_OUT_PLUS2

  • CLK_OUT_MINUS1

  • CLK_OUT_MINUS2

  • CLK_BUF_LOOP.

TP9CLK_SCLKBuffered version of serial data input clock to programmable oscillators
J7DXP and DXNTemperature sensing diode output. (There is not a socket fitted to the board, but you can fit a socket or measure the voltage directly from the socket pads.)
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