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3.5.3. JTAG signals

Figure 3.10 shows the pinout of the Multi-ICE connector and Table 3.3 provides a description of the JTAG and related signals.


In the description in Table 3.3, the term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan chain.Typically this is Multi-ICE, although hardware from other suppliers can also be used to debug ARM processors.

Figure 3.10. Multi-ICE connector pinout

Figure 3.10. Multi-ICE connector pinout
Multi-ICE signal description





Test reset (from JTAG equipment)

This active low open-collector is used to reset the JTAG port and the associated debug circuitry on the tile. It is asserted at power-up by each tile, and can be driven by the JTAG equipment. This signal is also used in configuration mode to control the programming pin (nPROG) on FPGAs.


Test data in

(from JTAG equipment)

TDI goes down to the motherboard and then up to the top tile in the stack. The signal connects each component in the scan chain.


Test mode select

(from JTAG equipment)

TMS controls transitions in the tap controller state machine. TMS connects to all JTAG components in the scan chain as the signal flows through the tile stack.


Test clock

(from JTAG equipment)

TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Buffers are used to reduce reflections and maintain good signal integrity. TCK flows up the stack of tiles and connects to each JTAG component. However, if there is a device in the scan chain that synchronizes TCK to some other clock, then all down-stream devices are connected to the RTCK signal on that component (see RTCK).


Return TCK

(to JTAG equipment)

Some devices sample TCK (for example a synthesizable core with only one clock), and this has the effect of delaying the time at which a component actually captures data. The RTCK signal is returned by the core to the JTAG equipment, and the clock is not advanced until the core has captured the data. Multi-ICE can be configured to wait for an edge on RTCK before changing TCK. In a multiple device JTAG chain, the RTCK output from a component connects to the TCK input of the next device in the chain. The RTCK signal on the tile connectors HDRB returns TCK to the JTAG equipment. If there are no synchronizing components in the scan chain then it is unnecessary to use the RTCK signal and it is connected to ground on the motherboard.


Test data out

(to JTAG equipment)

TDO is the return path of the data input signal TDI. The tile connectors HDRZ have three pins labeled TDI, TDO_IN, and TDO_OUT. TDI refers to data flowing up the stack and TDO to data flowing down the stack. The JTAG components are connected in the return path so that the length of track driven by the last component in the chain is kept as short as possible.


System reset (bidirectional)

nSRST is an active LOW open-collector signal which can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when a board has been reset by the user.

When the signal is driven LOW by the reset controller on the tile, the motherboard resets the whole system by driving nSYSRST LOW.

This is also used in configuration mode to control the initialization pin (nINIT) on the FPGAs.

Though not a JTAG signal, nSRST is described because it can be controlled by JTAG equipment.


Debug request

(from JTAG equipment)

DBGRQ is a request for the processor core to enter the debug state. It is provided for compatibility with third-party JTAG equipment.


Debug acknowledge

(to JTAG equipment)

DBGACK indicates to the debugger that the processor core has entered debug mode. It is provided for compatibility with third-party JTAG equipment.


Return TCK enable (from core tile to motherboard, not present on connector)

nRTCKEN is an active LOW signal driven by any core module or tile that requires RTCK to be routed back to the JTAG equipment. If nRTCKEN is HIGH, the motherboard drives RTCK LOW. If nRTCKEN is LOW, the motherboard drives the TCK signal back up the stack to the JTAG equipment.


All FPGAs configured (not present on connector)

GLOBAL_DONE is an open-collector signal that indicates when all FPGA configurations are complete. Although this signal is not a JTAG signal, it does effect nSRST. The GLOBAL_DONE signal is routed between all FPGAs in the system through the HDRB and HDRZ connectors. The master reset controller on the motherboard senses this signal and holds all the boards in reset (by driving nSRST LOW) until all FPGAs are configured.


Configuration enable

(from jumper on the Interface Module, not present on connector)

nCFGEN is an active LOW signal used to put the boards into configuration mode. The nCFGEN signal is routed between all FPGAs in the system through the HDRB connectors. In configuration mode all FPGAs and PLDs are connected to the scan chain so that they can be configured by the JTAG equipment.

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