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3.2. Reset control

Figure 3.1 shows the architecture of the reset circuitry. Figure 3.2 shows the power-on reset timing. In debug mode (see Debug mode), the following resets can be implemented in your design:

  • nSYSRST

  • nSYSPOR

  • D_nSRST

  • D_nTRST.

Figure 3.1. Reset and image loading control

Figure 3.1. Reset and image loading control

Figure 3.2. Power-on reset timing

Figure 3.2. Power-on reset timing

Note

The release time for GLOBAL_DONE depends on other boards in the system. It might be held low longer if other boards take longer to configure.

Table 3.1 describes the external reset signals.

Reset signal descriptions

Name

Description

Function

nPORESET

Power-on reset

This signal is used to generate the D_nTRST pulse at power on.

nSRST

System reset

nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when you have reset a board.

When the signal is driven LOW by the reset controller on the tile, the motherboard resets the whole system by driving nSYSRST LOW.

This is also used in configuration mode to control the initialization pin (nINIT) on the FPGAs.

Though not a JTAG signal, nSRST is described because it can be controlled by JTAG equipment.

Note

nSRST splits into two signals, D_nSRST and C_nSRST, to provide the debug and configuration signals on HDRZ.

nSYSRST

System reset

A system-wide, master reset signal from the platform board (for example the Integrator/AP and IM-LT1). This signal is typically used to reset ARM cores, peripherals and user logic. Can be activated from several sources, including GLOBAL_DONE=0. (See the Integrator/AP Motherboard User Guide or the Integrator/CP Compact Platform User Guide for further information on motherboard signals.)

FPGA_nPROG

Configuration reload

The FPGA_nPROG signal forces all FPGAs in the system to reconfigure.

GLOBAL_DONE

Configuration done

Open-collector signal that goes HIGH when all FPGAs have finished configuring. The system is held in reset until this signal goes HIGH.

nSYSPOR

Power-on resetThis is a post-configuration reset signal that is passed to all Logic Tiles in a stack. It is generated by analogue circuitry on the Interface Module. It can be used to reset user logic if required. It remains active for between 1 and 10µS after GLOBAL_DONE goes HIGH.

D_nTRST

TAP controller reset

A system-wide, open collector signal that can be driven LOW by Multi-ICE. This is the debug version of the nTRST signal.

It is connected to an FPGA input/output pin to provide a reset input to the virtual TAP controller. The Multi-ICE connector is the source of the D_nTRST signal.

D_nSRST

Multi-ICE system reset

A system-wide, open collector signal that can be driven LOW by Multi-ICE. This is the debug version of the nSRST signal.

C_nTRST

TAP controller reset

An open-collector signal that can be driven LOW by Multi-ICE when using the Progcards utility to program the Logic Tile FPGA. (This signal is connected to the PROG pin of the FPGA.) This is the config version of the nTRST signal.

C_nSRST

Multi-ICE system reset

A system-wide, open-collector signal. The Interface Tile shorts this signal to D_nSRST. This signal can be driven LOW by Multi-ICE when using the Progcards utility to program the Logic Tile FPGA. (This signal is connected to the INIT pin of the FPGA.) This is the config version of the nSRST signal.

Note

On the Integrator/AP, the expansion connector (EXPB) nSRST signal is completely separate from the core module (HDRB) nSRST signal (see the Integrator/AP User Guide for more details).