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A.4. Prototyping pads

Figure A.20 shows the layout of the prototyping pad area.

Figure A.20. Prototyping pad locations

Figure A.20. Prototyping pad locations

Table A.4 lists the signals on the prototyping pads. For more detail on the pads, see the Interface Tile schematic.

Note

Use the Peripheral Enable switch S1 to disable signals to the CAN, DAC, ADC, UART, I2C, USB, or IDE devices if you are using these signals on the prototyping pad.

Prototyping pad signals
Pad hole refSignal
A155V
A143V3
A13GND
A12-1Z[139:128]
A0GND
B155V
B143V3
BA13GND
B12-1Z[151:140]
B0GND
C155V
C143V3
C13-0GND
D155V
D143V3
D13GND
D12-1Z[163:152]
D0GND
E155V
E143V3
E13GND
E12-1Z[175:164]
E0GND
F155V
F143V3
F13-0GND
G15VCCOX
G143V3
G13GND
G12-1X[11:0]
G0GND
H15VCCOX
H143V3
H13GND
H12-1X[23:12]
H0GND
I15VCCOX
I143V3
I13-0GND
J15VCCOX
J143V3
J13GND
J12-1X[35:24]
J0GND
K15VCCOX
K143V3
K13GND
K12-1X[47:36]
K0GND
L15VCCOX
L143V3
L13-0GND
M15VCCOX
M143V3
M13GND
M12-1X[59:48]
M0GND
N15VCCOX
N143V3
N13GND
N12-1X[71:60]
N0GND
O15VCCOX
O143V3
O13-9GND
P15VCCOX
P143V3
P13GND
P12-1X[83:72]
P0GND
Q15VCCOX
Q143V3
Q13GND
Q12-1X[95:84]
Q0GND
R15VCCOX
R143V3
R13-0GND
S15VCCOY
S143V3
S13GND
S12-9SPARE[3:0]
S8-1X[103:96]
S0GND
T15VCCOY
T143V3
T13GND
T12-10Y[79:77]
T9-1SPARE[12:4]
T0GND
U15VCCOY
U143V3
U13-0GND
V155V
V143V3
V13GND
V12-1Y[91:80]
V0GND
W22-16GND
W155V
W143V3
W13GND
W12-1Y[103:92]
W0GND
X22EXT_CLK_POS_DN_IN
X21EXT_CLK_POS_UP_IN
X20CLK_GLOBAL_IN
X19B_CLK_POS_DN_OUT
X18B_CLK_POS_UP_OUT
X17CLK_GLOBAL_OUT
X16CLK_GLOBAL_nEN
X155V
X143V3
X13-0GND
Y22-15Y[135:128]
Y143V3
Y13GND
Y12-1Y[115:104]
Y0GND
Z22-15Y[143:136]
Z143V3
Z13GND
Z12-1Y[127:116]
Z0GND
AA22-15GND
AA143V3
AA13-0GND
AB22-15X[135:128]
AB143V3
AB13GND
AB12-1X[115:104]
AB0GND
AC22-15X[143:136]
AC143V3
AC13GND
AC12-1X[127:116]
AC0GND
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