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C.2.2. LCD power control

The LCD adaptor board accommodates a wide range of LCDs. Displays can require from 1 to 4 power supplies that can either be turned on/off simultaneously or need to be switched on/off in a certain order. System control register SYS_CLCD and the CLCD PrimeCell system register control power switching. The voltage supplies on the board are:


This is permanently on and is not switched. This provides power to the board (nominal 12V) for the backlight converter.


This supply is permanently on. It is generated from 5V.


The supply is generated from the 1.8V, 3.3V or 5V supply. It can be enabled by PWR3V5VSWITCH in SYS_CLCD or permanently enabled by link 13.


This supply is generated from 5V. It can be enabled by the CLPOWER signal in the CLCD PrimeCell control register or permanently enabled by link 15.


This -5V to -28V supply is generated from 5V. It can be enabled by VDDNEGSWITCH in SYS_CLCD or permanently enabled by link 14.


This 11V to 28V supply is generated from 5V. It can be controlled by the touchscreen D/A converter or manually with a pot. It can be enabled by VDDPOSSWITCH in SYS_CLCD or permanently enabled by link 11. This supply is used to generate the STN bias voltage.

LCD_IO_VDD and Buffer I/O voltage

This is the voltage to the interface logic on the adaptor board and the display. Link 16 selects the adaptor board interface level as CLPWR or FIXED. Link 3 selects the display interface level as SWITCHED_FIXED or SWITCHED_CLPWR.

Link 3 and link 16 must be set to use the same power source.


This is the voltage to the interface logic on the prototype board. Link 2 selects the level as 5V or 3.3V.


The I/O signals to the CLCD adaptor board pass through tri-state buffers. The buffers must be powered from the same IO voltage as that required by the CLCD. This enables the translation of the IO signals from the 3V3 signal levels present on the PB926EJ-S. The buffers are enabled by LCDIOON in SYS_CLCD.

Figure C.6 shows the block diagram of the adaptor board power-control circuitry.

Table C.2 shows the power configuration for the three displays. For additional information on configuring the CLCD displays, see the selftest code provided on the CD.

Table C.2. Power configuration
Voltage controlEpson 2.2Sanyo 3.8Sharp 8.4
SWITCHED_VDD_POSSoftware control15VSoftware control
Buffer enabled (software control)Always onAlways onSet from CLPOWER register in ARM926EJ-S PXP Development Chip

The links for power control are set during manufacture. Do not modify the links unless you are producing a new custom display board.

Use connector J4 to supply power to an inverter for a backlight. The backlight pins VIN are provide a nominal 12V supply. The backlight inverter must consume less than 5W. The I/O voltage level INV_IO is also present on J4. INV_IO can be link selected to be 5V or 3.3V.

In addition to voltage and ground pins, the connector also supplies the brightness adjustment voltage (0 to INV_IO voltage). The brightness is adjusted by a variable resistor, VR4, located near J4.

Figure C.6. CLCD buffer and power supply control links

Figure C.6. CLCD buffer and power supply control

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